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ISA-QMIPS
ISA-Eclipse
FS2 System Analyzers for
QuickLogic® QuickMIPS ESP Family and
Eclipse FPGA Devices
The System Analyzer supports the QuickMIPS ESP family which feature a MIPS Technologies MIPS32 4Kc microprocessor core. To learn more about the QuickLogic devices, go to this link: http://www.quicklogic.com
The analyzer provides complete run control debugging of the MIPS 4Kc CPU core in the QuickMIPS device. In addition to the run control and debugging features of the MIPS core, the analyzer features a Configurable Logic Analysis Monitor (CLAM) which allows the user to trace and trigger on up to 128 specified signals in the programmable logic fabric, with 32 captured simultaneously. In the internal trace system, all triggering and trace capture takes place on-chip in the QuickMIPS device. In the external trace version, trace is captured off-chip in the FS2 system analyzer, freeing up on-chip resources. The off-chip trace option also allows a richer trigger/trace feature set. The combination of logic analysis for the programmable fabric and run control for the embedded core makes this a powerful debug tool for the unique capabilities of the QuickMIPS device.
The system analyzer is contained in a compact chassis that connects to the QuickMIPS target system using a JTAG debug connector. The internal trace system uses a second 10-pin cable for the CLAM logic analysis functions. A high-speed 38-pin Mictor cable is used for trace capture with the external trace system. The system runs on a Windows® 98/NT/2000 PC over an IEEE-1284 EPP/ECP high-speed parallel port. The Accelerated Technology code|lab Debug or Green Hills MULTI debugger provide a source-level user interface.
The ISA-Eclipse System Analyzer supports the QuickLogic Eclipse family of FPGA devices. It has the same CLAM logic analyzer features in the QuickMIPS product, but without the MIPS core run control functions.
Key Features
Configurable logic analysis of any nodes within the QuickMIPS or Eclipse programmable fabric
Scalable number of triggers, width of trigger word, number of trigger states, number of event counters, and width of trace
Real-time trace output
Select up to 128 signals to monitor at compile time
Up to 32 channels and 4K frames trace buffer (on-chip trace)
128K frames trace buffer (with off-chip trace option)
Trigger conditions include high, low, dont care, rising, falling, either edge
One trigger-in/out signal to cross trigger with external instrumentation
MIPS-standard EJTAG hardware breakpoints and processor run control (QuickMIPS)
Read-write all processor registers and memory (QuickMIPS)
Go, halt processor run control (QuickMIPS)
Single step by assembly instruction or source line (QuickMIPS)
Unlimited software breakpoints (QuickMIPS)
Load code with symbols, including code, variables, and variable types (QuickMIPS)
Low-level access to JTAG functions for verification (QuickMIPS)
Flash programming support (QuickMIPS)
Single line assembler and disassembler (QuickMIPS)
Symbolic debug (QuickMIPS)
(QuickMIPS) indicates features only available with System Analyzer for QuickMIPS
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FS2 is a division of MIPS Technologies, Inc. © 2007 MIPS Technologies, Inc.
FS2, the FS2 First Silicon Solutions logo, FS2 Navigator, Bus Navigator, Logic Navigator, System Navigator, Clam, FPGAView, HyperDebug, HyperJTAG, MED,
and OCI are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries.
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