For complete technical information, download the datasheet here:

Full Spec Sheet, PDF


 

 

SNAV-HT80C51
System Navigator tools for Handshake Solutions
HT80C51 and HT80C51MX Clockless Microcontroller Cores

The HT80C51MX is the first clockless implementation of the 80C51MX (Memory eXtension) core. It combines the low power and easy system integration of Handshake Technology with the extended memory capabilities of the MX architecture to create an extremely versatile microcontroller core. Backwards compatible with the HT80C51 and functionally equivalent to clocked versions, it provides a seamless upgrade path for more advanced 8-bit applications. To visit the Handshake Solutions web site and learn more about the cores click here >>>.

The System Navigator probe is designed to support the special features and integrated peripherals of the Handshake Solutions HT80C51 and HT80C51MX cores. Special "silicon hooks" for System-on-Chip development have been integrated into the synthesizable IP model for the core. These On-Chip Instrumentation (OCI®) extensions allow FS2 to provide a powerful debug tool with advanced features at a competitive price.

The System Navigator probe hardware is contained in a compact chassis that connects to the target system using a standard 10 pin debug connector. It requires access to only 4 pins in the core processor. The system runs on a Windows® 2000/XP PC over an USB 2.0 or optional 10/100 Ethernet port. A graphical, source level debugger program provides an intuitive, easy to use interface. An optional Keil µVision3 software debugger interface is also available for complete compatibility with the Keil software tool chain.

Key Features
• Go, halt processor run control
• Supports bank switching and address memory extensions
• Access all HT80C51 and HT80C51MX processor registers, SFRs, extended SFRs, program memory, data memory, and internal data
• Unlimited software breakpoints for code in writable memory
• Scalable number of hardware execution breakpoints for code in non-writable memory
• Load binary, Hex or OMF51 file formats
• Complex triggers monitor address and data for code memory, internal/external data memory, internal/external SFRs
• Low-level access to JTAG functions for silicon verification
• Single line assembler/disassembler
• Optional trace display of assembly, source, or mixed assembly/source
• Optional break bus to synchronize multiple CPUs
• Symbolic debug including code, variables, and variable types
• Symbol Explorer provides hierarchical tree view of all symbols (modules, functions, blocks, variables, and more)
• Source window can display C, assembly, and mixed source code
• Source window provides execution control: go; halt; goto cursor; step over/into call
• Set or clear software or hardware breakpoints in source window
• Select global or local variables for watch window from the source window
• Trigger window allows triggers to be set on a combination of address, internal or external data, SFRs, and bus cycles
• Triggers can be set on an address range and/or data with masking bits
• Optional interface for Keil µVision2 software debugger
• Supports software tools from Keil, IAR and other vendors
 
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FS2 is a division of MIPS Technologies, Inc. 2008 MIPS Technologies, Inc.
FS2, the FS2 First Silicon Solutions logo, FS2 Navigator, Bus Navigator, Logic Navigator, System Navigator, Clam, FPGAView, HyperDebug, HyperJTAG, MED,
and OCI are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries.