FPGAView™ Software
Software for Configuring and Debugging Altera and Xilinx FPGA Devices
with Tektronix TLA Logic Analyzers and MSO Mixed Signal Oscilloscopes

The FPGAView™ software is a PC Windows-based program designed for use with Tektronix® TLA series Logic Analyzers and also with MSO 4000 series Mixed Signal Oscilloscopes. It enables real-time debugging of Altera® and Xilinx® FPGAs. Using FPGAView, design engineers can quickly and easily measure signals inside their FPGA design and select which group of internal signals to probe without having to recompile their design. FPGAView simplifies logic analyzer use by automatically updating channel names with the signal names extracted from the user's HDL (verilog or VHDL) code and providing a mechanism to auto-select channel groupings from the same selection.

With the TLA, the FPGAView software can be used in two scenarios; with the software installed and running on the Logic Analyzer exclusively and/or in conjunction with a separate Windows based PC. With the Tektronix Logic Analyzer use model, the FS2 FPGAView software is running exclusively on the TLA. In the mixed logic analyzer / PC mode, the FPGAView software is run from the user's Windows based PC, and the TLA located in a remote lab is also interfaced from the user's PC.

When used with an MSO4000 series oscilloscope, the FPGAView software is installed and run from a PC host which communicates with the MSO over a USB or Ethernet link.

FPGAView software makes debugging your FPGA design faster than ever, because the once tedious process of defining and routing the FPGA signals to the external logic analyzer connector and mapping channels for the logic analyzer are all handled by the FPGAView software. To learn more about the Tektronix Logic Analyzers, visit the web site at www.tektronix.com

The FPGAView software package works with a Tektronix TLA 600, 700, 5000 or 7000 series with Tektronix logic analyzer software version 4.3 or later or Tektronix MSO4000 series oscilloscope.

For Altera FPGAs it requires the appropriate JTAG probe for controlling the device - either an FS2 System Navigator probe, Altera ByteBlaster or USB Blaster. It also requires the use of Altera Quartus II 5.1 or later.

Key Features for Altera devices
 • Speeds debugging of Altera FPGA devices with the Tektronix Logic Analyzer or Mixed Signal Oscilloscope
• Convenient control of the Altera FPGA Logic Analyzer Interface (LAI) logic block bank selection
• Identify and map LAI output pins to external logic analyzer connector faster than ever
• Automatic update of channel names when selecting a different signal bank
• Complete flexibility in hardware probe use
• Works with Altera USB Blaster, ByteBlaster or FS2 System Navigator probes for JTAG interface
• Supports the Altera Cyclone, Cyclone II, Stratix, Stratix II, and APEX FPGAs
• Same software whether used on a TLA or PC
• Handles multiple LAI instantiations in one device for multiple clock domain support
• Supports multiple FPGA devices through JTAG chaining
• PC Windows user interface
• User can assign a TLA setup file for each Bank, making it easy and automatic to reconfigure channel groupings

For Xilinx FPGAs, FPGAView controls the device with the Xilinx Platform Cable USB and requires ISE version 8.2i or later to be installed on the Windows PC that is running FPGAView.

Key Features for Xilinx devices
 • Speeds debugging of Xilinx FPGA devices with the Tektronix TLA Logic Analyzer or MSO4000 Mixed Signal Scope
• Uses OCIGen (On-chip Instrumentation Generator) program to install the LA Core and wire up signals to it
• Supports the Xilinx Vertex, Virtex2, Virtex4, Virtex 5, Spartan2, Spartan3, and Spartan3E FPGAs
• Supports more than one device on the JTAG scan chain, identifying correct devices and controlling the appropriate one
• Automatically updates TLA or MSO channel names when selecting different signal banks
• PC Windows user interface
• Updates channel names for the MS4000 series from a host PC when connected over USB or Ethernet
• User can assign a TLA setup file for each bank, making it easy and automatic to reconfigure channel groupings
• State (synchronous) or Timing (asynchronous)acquisition modes
• Supports 1,2,4,8..64 signal banks
• Supports from 4 to 128 signals per bank
• Rising or falling clock edge selection
• Registered or unregistered inputs to assist in meeting timing closure
• Includes General Purpose Inputs and Outputs (GP I/O) selectable in groups of 8 bits up to 64 bits
• Works with Xilinx Platform Cable USB, a JTAG probe (or on-board embedded Xilinx programmer) to control the LA Core multiplexer

 
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FS2 is a division of MIPS Technologies, Inc. © 2007 MIPS Technologies, Inc.
FS2, the FS2 First Silicon Solutions logo, FS2 Navigator, Bus Navigator, Logic Navigator, System Navigator, Clam, FPGAView, HyperDebug, HyperJTAG, MED,
and OCI are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries.