NEW INDUSTRY CONSORTIUM TACKLES SILICON DEBUG
Companies collaborate to define requirements and accelerate adoption of
design-for-debug methodologies

ANAHEIM, Calif., June 14, 2005 — Representatives from the semiconductor design, manufacturing test and silicon debug supply chain announced formation of the Design-for-Debug (DFD) Consortium (www.designfordebug.org) at an open meeting held on June 13, 2005 during the 42nd Design Automation Conference (DAC) in Anaheim, Calif. Consortium members and conference attendees gathered at the kick-off session to initiate an industry-wide discussion of silicon debug challenges and a collaborative approach for defining DFD solutions.

The DFD Consortium is initially focused on mobilizing a representative cross-section of the industry to raise awareness and create a forum in which tool interoperability and methodology issues can be identified and investigated. The DFD Consortium will also identify data and file format standards required to simplify and accelerate the functional debug of chips mounted in silicon prototypes or systems (referred to as “in situ”). These efforts are all targeted at providing both DFD users and solution providers with a better understanding of product requirements and practical roadmap for adopting design guidelines.

Charter members include: Corelis, Inc.; DAFCA, Inc.; First Silicon Solutions (FS2); Intellitech Corporation; JTAG Technologies; Fidel Muradali (consultant) and Novas Software, Inc. Consortium organizers are engaged in discussions with industry organizations, and also actively encouraging participation of electronic design automation (EDA), automated test equipment (ATE), and design for test (DFT) providers as well as semiconductor and systems companies involved in the development and adoption of emerging DFD methodologies, software tools, and intellectual property offerings.

“The time needed to track down functional problems once a chip is in its prototype system is unpredictable and costly today, mainly because a broad set of silicon debug and diagnosis solutions is not yet commercially available,” commented Fidel Muradali, program chair, International Silicon Debug and Diagnosis Workshop. “This cross-company consortium is valuable because it brings the focus needed to define practical solutions and methodologies that can bridge the design and manufacturing test domains.”

Design for Debug

Due to the rise in design complexity, deep sub-micron effects on signal integrity and semiconductor manufacturing process variations, functional errors as well as performance shortcomings have become endemic in first-silicon prototypes. Inherent in testing a chip “in situ” is the tremendously limited access to internal signals and visibility into the silicon device itself. This makes the process of isolating and analyzing silicon problems extremely tedious and time consuming. It is also increasingly more difficult to quickly determine whether they are undetected functional design bugs or physical manufacturing defects.

Existing silicon debug methods are ad hoc and require significant resources to gain the smallest insight into the silicon. A multitude of tools and steps are utilized to narrow the scope of the search before the results can be manually mapped back to the design. Due to the improvised nature of this approach, the debug of silicon has become a major bottleneck in reaching volume production.

The design-for-debug approach encompasses: 1) the implementation of on-chip logic to enhance the ability to retrieve crucial data through improved design observability; and 2) the extrapolation of the limited retrievable data using process automation and analysis techniques for system-level silicon validation. The commercial development of well-defined DFD methodologies and interoperable tool suites has the potential to significantly improve the efficiency of silicon debug, lower development costs and accelerate time-to-volume production for integrated device manufacturers.

About the DFD Consortium

The Design-for-Debug Consortium was created to define and promote the products, methodologies and industry standards required for more efficient functional debug of silicon prototypes. The DFD Consortium welcomes industry participation by EDA, ATE and DFT providers, as well as system and semiconductor companies, with membership that today includes: Corelis, Inc.; DAFCA, Inc.; First Silicon Solutions (FS2); Intellitech Corporation; JTAG Technologies; Fidel Muradali (consultant) and Novas Software, Inc. For more information or to become a member of the DFD Consortium, visit (www.designfordebug.org).

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